Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (“PROM”), which uses word line—bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices, such as the floating gate avalanche injection metal oxide semiconductor transistor to store logical information. PROM typically is not reprogrammable.
One example of a PROM cell that uses the breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in U.S. Pat. No. 6,215,140, issued Apr. 10, 2001 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series combination of an oxide capacitor and a junction diode as the crosspoint element. An intact capacitor represents the logic value 0, and an electrically broken-down capacitor represents the logic value 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operation specifications. Silicon dioxide has a breakdown charge of about 10 C/cm2 (Coulomb/cm2). If a voltage of 10 volts is applied to a capacitor dielectric with a thickness of 10 nm (resultant field strength 10 mV/cm), a current of about 1 mA/cm2 flows. With 10 volts, this results in a substantial amount of time for programming a memory cell. However, it is more advantageous to design the capacitor dielectric to be thinner, in order to reduce the high power loss that occurs during electrical breakdown. For example, a memory cell configuration having a capacitor dielectric with a thickness of 3 to 4 nm can be operated at about 1.5 V. The capacitor dielectric does not yet break down at this voltage, and thus 1.5 V is sufficient to read data from the memory cell. Data are stored, for example, at 5 V, in which case one cell strand in a memory cell configuration can be programmed within about 1 ms. The programming speed can be changed depending on permissible power losses.
Some types of nonvolatile memory are capable of being repeatedly programmed and erased, including erasable programmable read-only semiconductor memory, generally known as EPROM, and electrically erasable programmable read-only semiconductor memory, generally known as EEPROM. EPROM memory is erased by applying ultraviolet light and programmed by applying various voltages, while EEPROM memory is both erased and programmed by applying various voltages. EPROMs and EEPROMs have suitable structures, generally known as floating gates, that are charged or discharged in accordance with data to be stored thereon. The charge on the floating gate establishes the threshold voltage, or VT, of the device, which is sensed when the memory is read to determine the data stored therein.
A device known as a metal nitride oxide silicon (“MNOS”) device has a channel located in silicon between a source and drain and overlain by a gate structure that includes a silicon dioxide layer, a silicon nitride layer, and an aluminum layer. The MNOS device is capable of switching between two threshold voltage states VTH(high) and VTH(low) by applying suitable voltage pulses to the gate, which causes electrons to be trapped in the oxide-nitride gate (VTH(high)) or driven out of the oxide-nitride gate (VTH(low)).
A semiconductor memory cell that uses dielectric breakdown to store digital data is disclosed in U.S. Pat. No. 6,798,693, issued Sep. 28, 2004 and assigned to the assignee of the current application, which is hereby incorporated by reference. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The memory cell stores information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. The ultra-thin dielectric could include, for example, a high-quality gate oxide of about 50 Å thickness or less, as is commonly available from presently available advanced CMOS logic processes.